1. Field of the Invention
The present invention relates to a memory architecture.
The invention particularly, but not exclusively, relates to a memory architecture of the FLASH-NOR type using a so called ramp reading method and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, a new reading method has been recently proposed for FLASH-NOR memories called “ramp reading method”.
This reading method and the corresponding memory device is described for example in U.S. Pat. No. 7,054,197.
The reading method described in this document provides to apply, in a reading step, a same voltage linear ramp both on the word lines WL of the matrix cells of the memory device and on the word lines WL of the corresponding reference cells. As it is well known, in memory cell matrixes the word lines WL connect the gate terminals of the cells.
The method thus comprises a comparison step between a time instant in which a given matrix cell reaches a predetermined drain current and a time instant in which a given reference cell reaches the same drain current.
In practice, the matrix cell read and the reference cell are compared not through the current absorbed by them but through their threshold voltage.
The principle scheme of the ramp reading method described in the above cited U.S. patent application is reported in FIG. 1.
In particular, in this figure, a generic matrix cell 1 with MOS transistor has a source terminal connected to a source line SL and a drain terminal connected to a bitline BL. Moreover, the MOS transistor has a control terminal connected to a wordline WL, which receives a voltage ramp.
The bitline BL is also connected to a first input terminal, in particular an inverting input terminal (−), of a precharge I/V converter 2 having a second input terminal, in particular a non-inverting input terminal (+), receiving a reference voltage VREF and an output terminal OUT1 connected to a first input terminal, in particular a non-inverting input terminal (+), of a comparator 3.
The bitline BL is further connected, by a current mirror 4, to a reference current generator IREF, the current mirror 4 being in turn connected to a first voltage reference, in particular a supply voltage reference Vcc and the reference current generator IREF being in turn connected to a second voltage reference, in particular a ground GND.
The comparator 3 comprises a second input terminal, in particular an inverting input terminal (−), connected to the first input terminal of the precharge I/V converter 2, as well as an output terminal OUT2 connected to a bank of latch registers LT. Moreover, the input terminals of the comparator 3 are connected to each other by a resistive element R0.
Finally, the latch registers LT are connected to a references bus REF_BUS and output a value CV corresponding to the logic value of the cell 1 as read.
A particular memory partition architecture, as schematically shown in FIG. 2 and globally indicated with 10, corresponds to this ramp reading method.
The architecture 10 comprises a matrix 5 of memory cells, in particular multilevel cells.
It is remembered that the reading and verify of the content of multilevel cells use at least one first R1, one second R2 and one third read reference R3, as well as one first P1, one second P2 and one third programming reference P3, together with a deplete state verify reference DV and an erase verify reference EV, as schematically shown in FIG. 3.
The matrix 5 is then connected to a row decoder 6 arranged along a first side of the matrix 5 of the memory cells and an array 7 of reference cells arranged along a second side of the matrix 5 of memory cells, opposed to the first side.
In particular, the row decoder 6 comprises at least one first ramp generator RG1 connected to the cells of the matrix 5 by means of a matrix wordline WLmat, as well as a second ramp generator RG2 connected to the array 7 of reference cells by means of a reference wordline WLref.
The architecture 10 also comprises a first detector block 8, arranged along a third side of the matrix 5 of memory cells, this third side being perpendicular to the first and to the second side of the matrix 5. The detector block 8 comprises, in particular, a plurality of sense amplifiers SA1 . . . SAn connected at the input to the cells of the matrix 5 and at the output to a plurality of latch registers SAL1 . . . SALn.
The latch registers SAL1 . . . SALn are connected to each other by a third references bus REF_BUS, which further connects them also to a reference sense amplifier SAref comprised into a second detector block 9. The second detector block 9 is placed next to the first detector block 8 in correspondence with the second side of the matrix 5 of memory cells.
It is to be noted that, a first dimension X corresponding to the extension direction of the rows of the matrix 5 and a second direction Y corresponding to the extension direction of the columns of the matrix 5 being defined, it results that:                the row decoder 6 and the array 7 of reference cells have sizes comparable to the one of the matrix 5 of memory cells in the second direction Y;        the first detector block 8 has a size comparable to the one of the matrix 5 of memory cells in the first direction X;        the second detector block 9 has a size comparable to the one of the array 7 of reference cells in the first direction X; and        the first detector block 8 has a size comparable to the one of the second detector block 9 in the second direction Y.        
The ramp reading method described in the U.S. patent application above indicated and implemented by the architecture 10 shown in FIG. 2 shows many advantages, but, being of the dynamic type, introduces a series of new and non-negligible problems.
In particular, in the case of multilevel memory cells, where the application of the voltage ramp reading method is particularly indicated, the control of the threshold voltage values of the reference used in reading and verify is problematic.
Further problems can be summarized in:
superfluous time in reading;
variability of the access time in reading; and
mismatch between verify voltage ramp and reading voltage ramp.
The accuracy of the memory device in reading and verify as well as its stability with respect to the working conditions in which the memory device must ensure a correct operation are also of particular interest.
In particular, the accuracy of the memory device generally depends on the supply voltage and on the working temperature of the device itself.
It is also important to consider that erasing, programming and reading operations of a given memory portion are carried out at different times and can thus be carried out under different working conditions.
In general, the prior art thus needs to define voltage margins between the various distributions on the basis of the worse case, which typically consists in programming at a certain temperature/voltage and reading at another temperature/voltage.